So the idea is to take components that are often separate on a system processors, main memory, networking and other peripherals and etch them all onto chips and then stack them up in a 3D array, rather than solder them onto a motherboard and wire them together with metal stripes in a 2D array. By going 3D, the wires between components can not only be shortened - cutting the time those components need to exchange signals and potentially requiring less energy to send a signal.
"Today's chips, including those containing 3D transistors, are in fact 2D chips that are still very flat structures," explained Bernie Meyerson, a vice president of IBM Research, in a statement announcing the partnership between Big Blue and 3M.
"Our scientists are aiming to develop materials that will allow us to package tremendous amounts of computing power into a new form factor a silicon skyscraper. We believe we can advance the state-of-art in packaging, and create a new class of semiconductors that offer more speed and capabilities while they keep power usage low key requirements for many manufacturers, especially for makers of tablets and smartphones."
The initial plan is to come up with a way to stack up as many as 100 chips into a tower of computing power. Over the long haul IBM wants to be able to bond stacks of complete wafers together, bonding hundreds of processors at a time.
The plan, says the IBM source, is to get it into production around the end of 2013.
http://www.theregister.co.uk/2011/09/07/ibm_3m_3d_chip/For now this is just secret sauce for IBM and 3M, but applied to GPU's or ASIC's could increase hashing power while keeping power consumption low.