I'm not an electrical engineer, so probably someone who is will shit all over this.  Anyway.

I think these chips are small and probably on 90-130 nm technology.

SHA256 hashing requires about 13,500 logic gates per circuit or 27,000 transistors.  An AMD K8 130 nm CPU has about 106M transistors in 100mm^2 with a TDP of 60W, so we could fit about 3926 SHA256 hashing circuits on one of these ASIC dies.  These hashing units run at 65 cycles per hash; we would expect from an immature 130 nm process for the ASIC that clock rates of 1 GHz would be achievable.  This would mean 14.5 MH/s per hashing circuit or 56.9 GH/s per 100mm^2 die with a 60W power consumption.

How does that compare to what has been given to us by BFL?  The BFL single, which is assumed to be a single die, is rated at 40GH/s.  With the above ignoring crucial things like transistors for I/O, it does indeed seem possible that the BFL single can provide 40GH/s at 60W on a 130 nm process.