Update

Chip Specification
Technology Summary:
  130 nm
  1 Ploy
  6 Metal
  1 Top Metal
  Logic Process
Core Voltage: 1.2 V
I/O Voltage: 3.3 V
Core Frequency: 335 MHz
Core Frequency Range: 255-378 MHz
PLL Multiplier: 28
Power Consumption: 4.2 J/GHash
Number of Pads: 40
  22 Data
  18 Power
Package Type: QFN40
Packaged Chip Size: 6 mm x 6 mm

Chip Interface
Data Pins (22 in total):

clk                    i
soft-reset             i
reset                  i
cs                     i
addr[6]                i
data[8]                i/o
w_valid                i
w_allow                o
r_allow                o
r_req                  i

Address Allocation:

0-31    writing midstate
32-43   writing data
44-47   reading nonce