I think there is confusion between MH/s (mega hash per second) with MHz (mega hertz, clock frequency).
No.
Current implementations are made so each clock does one "turn" of the sha256 algorithm, but on multiple stages, usually 128 to make a complete 2-sha256 bitcoin full computation (sometimes called a "stack" )
So 1 chip with one complete stack gives 1 complete computation each clock in such implementations, and therefore Mhz = MH/s
That was my question : is there only one stack in this chip ?
If you had 2 stacks in the chip, you would have had MH/s = 2* MHz
This is only true for most of the used designs. At least bitfury has the sea of hashers aproach where each hashing core needs 68? cycles to compute a hash but it turned out that it allows a more effective device utilisation.
As far i understand the discussion between bitfury and friedcat the sea of hashers aproach was at least taken into account.
Maybe friedcat could produce a prelininary datasheet that would be sufficient to design a pcb. I am curious if the pll multipliert is fixed which would finetuning for each chip would be a little more complicated than just setting a register.