Re: [ANN] Spondoolies-Tech - carrier grade, data center ready mining rigs
This checkerboard pattern is not "making life easier at the silicon level". It is a symptom of using completely invalid approximate model of parasitic components and then using those approximated, but not really existing, parasitics as an additional power decoupling filter.
It's the exhibition of the symptom - but the cause thereof leads to that layout as it is. Laziness/not having to deal with intricacies also makes life easier 
I'm not sure if I understood your 2nd paragraph. It seems like you think I proposed using two different pad pitches: one denser for the chip and one coarser for the board. What I intended to convey is using the same pad pitch on both chips and board.
No, not at all. I was referring to some of Intel's chips that actually have different BGA pitches on the same package as an example of some of the really oddball BGA designs some companies throw out there as a comparison point for alternating+side of I/O not being the worst, albeit not ideal either.