Thanks for the transparency, but the unpackaged die size is what you ought to be posting.  Without that it's impossible to make performance comparisons (or at least those comparisons would have to assume it fills the whole package cavity, which portrays Avalon in the worst possible light).  Please provide the unpackaged die size.

Also, I think you may have neglected to say how many of these chips are in the 60GH/s device… or perhaps I missed that.  Anyways, without knowing how many chips are in the device, none of the information above is really useful.  Did you post this somewhere that I didn't see?



Interesting; an FO4 on TSMC 110nm is around 63ps, so at your 3.9ns cycle time (256mhz cycle rate) gives a datapath that is 62 FO4's deep.  Of course that doesn't mean there are 62 levels of logic!  Wire delays and clock skew (for chips that have clocks) come out of this budget too.