I didn't read the last 2 pages but I wanted to give my opinion of what is happening, it's either:

1. Ram Latency is being reduced (as was already mentioned)

2. Clock dividers being used between core and memory are hitting a favorable divider at the "sweet spot", favorable meaning most efficient


This kind of thing used to happen for example on p35 chipsets, there were some bus frequencies that while lower, were faster due to "memory latches" (latencies used) and ram dividers