Having personally worked on a project where our final product was an ASIC I can tell you that your chances of having a working first piece are almost zero.

You get everything working in Verilog on your FPGA development board and send the Verilog files to the fab.  They do the layout, make the masks, produce the first lot, do testing, ship you the first parts.  You get the parts and damn, guess what you forgot something dumb.  So it's back to the fab with rev 2 of the Verilog files.