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Re: Butterfly Labs November Update (ASIC Chips are "flawed". Delays.)
by
BFL-Engineer
on 28/11/2012, 14:42:08 UTC
Hi Everyone,

We've been very busy recently, unfortunately I couldn't catch up with the forums. There is a correction to be made: Chips are not and were not flawed. We decided to add certain clock buffers to improve noise-resistance and possibly increase frequency even further. The improve in noise resistance was our real goal (average frequency increase across a full wafer can be a bi-product). The decision was made to increase the near 100% chance of success even more. We'll keep you posted. If you had any questions, please let us know.


Regards,
Nasser