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Re: Butterfly Labs November Update (ASIC Chips are "flawed". Delays.)
by
crazyates
on 28/11/2012, 21:40:08 UTC
Okay, so 'BFL-Josh' says 'There was a flaw in the chip that needed to be addressed' .. and now there isn't? Get on the same page, people.
To someone like me, there's a very small difference between "Engineering oversight" and "Design flaw".