In VLSI design there is the concept of fan-out, which is the the number of gates that a gate has to drive. The larger the load on a gate, the more capacitance slows the rise and fall of the signal edge. You can't just take a clock source and hook it up to a couple hundred points around the chip as the capacitance is such that a minimum sized transistor can't drive it. You can increase the drive capability of the circuit by cascading stages making each stage about 4x larger that the last (see FO4) and by buffering the signal. Just increasing the drive capability of your main clock source isn't always the best answer though, and local clock buffers are often used for different logic blocks. It's basically two inverters in series. They aren't a cure-all though. You still run into skew, where the signal from your clock source arrives later at one part of the chip than another, and jitter, where the period of the clock isn't regular. If they already have a working design "without flaws", they better be damned careful adding clock buffers. Depending on how synchronous the design is, it's not trivial to change a lot in your clocking system without introducing new problems.
This (emphasis added). You don't screw around with the clock tree unless you absolutely have to.
You should take Elden's words with a grain of salt. He's pretty smart, but has a history of just talking out his ass, as evidenced by the fact that he just makes stuff up as he goes along:
It's utterly pointless to compare a standard-cell design to a full-custom design using transistor count. Even between full-custom designs it's normal to see a 4x variation in area based on the foresight of the architect and the skill of the layout designer. By the way, BFL doesn't use the phrase "full custom" to mean the same thing it means in the industry.
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By the way, BFL doesn't use the phrase "full custom" to mean the same thing it means in the industry.
We don't? Please elaborate. (I'm serious, I'm not being snarky. If we/I am using it incorrectly, then I would like to use the proper term.)
Standard-cell ASICs and synthesis-flow ASICs are not considered full-custom chips.
The phrase "fully custom" is a BFL-ism that sounds a lot like "truthiness"
In fact the third google hit for "fully custom asic" on the entire interweb is BFL which ought to be a hint that it is a contortion of the usual industry terminology...Emphasis mine. (Google "Fully Custom ASIC". 14k results, most of them not BFL. The ones that are BFL? Someone else wrote it. (https://bitcointalk.org/index.php?topic=83985.0))