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Re: Just what is a clock buffer anyway?
by
Inaba
on 01/12/2012, 16:21:15 UTC
Elden as to his BS about how BFL isn't using a full custom ASIC

I never said that.


Are you a pathological liar or something?  Are you denying you wrote this?

It's utterly pointless to compare a standard-cell design to a full-custom design using transistor count.  Even between full-custom designs it's normal to see a 4x variation in area based on the foresight of the architect and the skill of the layout designer.  By the way, BFL doesn't use the phrase "full custom" to mean the same thing it means in the industry.


Quote
By the way, BFL doesn't use the phrase "full custom" to mean the same thing it means in the industry.

We don't?  Please elaborate. (I'm serious, I'm not being snarky.  If we/I am using it incorrectly, then I would like to use the proper term.)

Standard-cell ASICs and synthesis-flow ASICs are not considered full-custom chips.

The phrase "fully custom" is a BFL-ism that sounds a lot like "truthiness" Smiley  In fact the third google hit for "fully custom asic" on the entire interweb is BFL which ought to be a hint that it is a contortion of the usual industry terminology...

I asked you point blank if we are not using the phrase "full custom" correctly to describe our chips, what is wrong with it.  You proceeded to explain that what BFL was describing was a Standard-cell ASIC and/or synthesis-flow ASIC.  Ok, so I guess I missed a reason as to why you post such nonsense:  You a) Have an agenda, b) Don't know what you're talking about or c) are a pathological liar. 

I guess it's up for grabs which one.