There are already smaller process sizes in use today, for those with deep enough pockets. Intel's Ivy Bridge chips use a 22nm process, vs BFL's 65nm. Remember that the size advantage saves space in two dimensions, such that halving the process size results in a quartering of the die area.
Another redesign possibility is on the logic level, designing the hashing engines to fit into a smaller die area, to scale to higher clock speeds, and most importantly, to consume less energy.
There are probably also other areas where the design can be improved upon, such as improved thermal coupling of the chip die to the chip package. Using a flip-chip design for instance.
65nm is the smallest process any other small company making fully custom designed chips in any industry can be expected to use. Intel designs and produces on a scale that justifies not needing to outsource their chip fabrication, for example. I'm not saying Intel is better than BFL, but only that they might have some resources that are not accessible to companies producing at BFL's level. It is after all an application specific chip, and that application is hashing.
Who knows what the final chip package will be? There might be changes to that too, but to expect smaller than 65nm - when a few months ago the speculation was that no small company like BFL could afford to go 65nm? I just want to press fast forward to about 2 weeks from now when the picture is more than clear on how things stand with the various ASIC offerings and initial shipment.