Post
Topic
Board Hardware
Re: The performance claims and prices are unrealistic
by
pcm81
on 28/01/2013, 04:19:35 UTC
]I actually did a standard cell design for a miner last year myself, starting from RTL generated off one of the open source HDL designs.  God knows if it would have actually run at an acceptable clock rate— given that I don't really know what I'm doing... but it wasn't that much work to get _something_.  A miner is insanely repetitive. The hash function is very simple. Thank god for design automation.

Congratulations, you programmed an FPGA. This is not the same as designing a true ASIC implementation.