@TheSeven: thanks for providing the vhdl sources. i am currently porting it to an atlys board (which is quite trivial) but the completely unrolled version is not fitting. do you already ported the configurable version to vhdl?
I didn't get around to making this configurable, but I made a smaller one manually earlier today, which is completely untested though.
Hm, I might as well just have a shot at a configurable one right now.
Actually I might offer to make a custom-made optimized fpga images (bit file) for Xilinx FPGAs for an adequate amount of bitcoins, if people want me to...