I remember that someone discussed before, going from a 110nm process to 65nm process in principle won't generate a 80% increase in efficiency, the best estimate is around 50%. There was a possibility that Avalon had an unefficient design, then BFL might gain another 30% efficiency by using a better design
In principle going from 110nm to 65nm reduces power consumption by 65% (1-(65/110)**2 because power efficiency is proportional to the inverse of the square of the feature size).
But the process node is not everything. Consider ASICMINER for example: they have chips that are more power efficient than Avalon, despite the worse process node (respectively 130nm vs 110nm). ASICMINER does 167 Mhash/Joule vs Avalon doing only 150 Mhash/Joule.