Phew! After a couple of weeks of learning FPGAs, here is my port of the "Official" FPGA miner to Xilinx chips, using the serial port for communications:

http://iki.fi/teknohog/hacks/software/xilinx-serial-miner.zip

I have tried to make only minimal changes to the original Verilog code. The communication could probably use some error checking, but it's a "works for me" first release, with a few accepted shares in a pool.

Unfortunately, my Spartan3E 500K has to keep the loop unrolling to a minimum.