You are incorrect. Cache lines are 64-bytes long because AMD memory channels are 64-bits wide (i.e. 2 DDR5 chips). The GCN memory controller is not 32-bits wide, with 2 consecutive bursts to fill a cache line.
"Each memory controller is 64-bits wide and composed of two independent 32-bit GDDR5 memory channels." - pg 10:
https://www.amd.com/Documents/GCN_Architecture_whitepaper.pdf
"Each memory controller is 64-bits wide and composed of two independent 32-bit GDDR5 memory channels." - pg 10:
https://www.amd.com/Documents/GCN_Architecture_whitepaper.pdf
I read tons and tons of docs (including this whitepaper), but somehow missed that one line. Ok. Misconception clarified
