Re: Official Open Source FPGA Bitcoin Miner (Smaller Devices Now Supported!)
trying to build a depth:=3 version right now.
slice luts: 54% (53% used as logic)
slice registers: 26%
occupied slices: 66%
estimates after synthesis.
Sounds like depth:=4 might be achievableslice luts: 54% (53% used as logic)
slice registers: 26%
occupied slices: 66%
estimates after synthesis.
with a targeted 50mhz clock p&r takes forever and finally fails with setup violations.
problem is congestion/routing, not available ressources in terms of FFs or LUTs...
Sounds like Spartan6 routing is just crap.problem is congestion/routing, not available ressources in terms of FFs or LUTs...
You might want to try depth:=2 and depth:=3 with doubled registers in the pipeline stages to allow for retiming and thus hitting higher frequencys, at the expense of a couple of flipflops, which you seem to have plenty of.
if you have the time, then just give it a try for xc6slx45-2csg324 with 50mhz and depth:=3
No, being busy synthesizing a XC6VLX760 design, this will take a while.increasing the frequency is not an option, with depth:=2 the timing performance design goal reports just 55mhz after p&r.
This sounds like you might want to try the following:- Split the sha256 rounds into two pipeline stages, as stated above (retiming)
- Experiment with various design strategies. For some reason "Runtime optimized" seems to yield the best results for this design. If you have the time, try SmartXplorer
- If all this doesn't work out, run it at 55MHz instead of 50, should bring it to 3.6MH/s
