Code:
$ ./strap -c trc:60 -c trcdw:13 -c trcdwa:13 -c trrd:5 -c tcl:20 -c tr2w:28 -c tw2r:15 -c trfc:145 -c trprda:11 -c trpwra:46
REGISTER KEY VALUE NEWVALUE
RAS trc 61 60
RAS trcdr 20 20
RAS trcdra 20 20
RAS trcdw 14 13
RAS trcdwa 14 13
RAS trrd 6 5
RAS unused1 0 0
CAS tcl 18 20
CAS tnopr 0 0
CAS tnopw 0 0
CAS tr2r 5 5
CAS tr2w 25 28
CAS tw2r 17 15
CAS unused1 2 2
CAS unused2 0 0
CAS unused3 0 0
MISC trfc 148 145
MISC trp 9 9
MISC trprda 11 11
MISC trpwra 48 46
MISC unused1 0 0
MISC unused2 1 1
MISC unused3 0 0
Old Strap => 777000000000000022339D00CE516A3D9055111230CB4409004AE600740114206A8900A002003120150F292F94273116
New Strap => 777000000000000022339D00AD515A3CC0550F142ECB1409004AE600740114206A8900A002003120150F292F94273116
REGISTER KEY VALUE NEWVALUE
RAS trc 61 60
RAS trcdr 20 20
RAS trcdra 20 20
RAS trcdw 14 13
RAS trcdwa 14 13
RAS trrd 6 5
RAS unused1 0 0
CAS tcl 18 20
CAS tnopr 0 0
CAS tnopw 0 0
CAS tr2r 5 5
CAS tr2w 25 28
CAS tw2r 17 15
CAS unused1 2 2
CAS unused2 0 0
CAS unused3 0 0
MISC trfc 148 145
MISC trp 9 9
MISC trprda 11 11
MISC trpwra 48 46
MISC unused1 0 0
MISC unused2 1 1
MISC unused3 0 0
Old Strap => 777000000000000022339D00CE516A3D9055111230CB4409004AE600740114206A8900A002003120150F292F94273116
New Strap => 777000000000000022339D00AD515A3CC0550F142ECB1409004AE600740114206A8900A002003120150F292F94273116
What could possibly go wrong!
shouldn't we be decreasing tcl to make it tighter?
I know this is not apples to apples because I'm looking at a 1750mhz strap from a 470 vs a 480, but you'll see higher tCL on both boysie's and heliox's 480 mods...
Code:
----------------------------------------------------------------------------------------------------
Strap (CAS) tcl tnopr tnopw tr2r tr2w tw2r
----------------------------------------------------------------------------------------------------
480-boysie2000 21 0 0 5 29 15
480-heliox2000 22 0 0 5 29 16
MSI-470-Hynix-Stock-1750 19 0 0 5 25 19
----------------------------------------------------------------------------------------------------
Strap (CAS) tcl tnopr tnopw tr2r tr2w tw2r
----------------------------------------------------------------------------------------------------
480-boysie2000 21 0 0 5 29 15
480-heliox2000 22 0 0 5 29 16
MSI-470-Hynix-Stock-1750 19 0 0 5 25 19
----------------------------------------------------------------------------------------------------
So, thats what I was basing it off of.
If someone has the strap tables handy from a rx480, I'll be happy to re-run the numbers.
Currently RX480s get > 30mh when we use straps from 1625 or 1500. Latency on those are 15-16 as I remember. Without changing anything if you can get tcl down to 16 and tighten the timings that are based on tcl+some other timeing tightened by 3-4 clock rounds. That should give you mininal change rom. Just tcl and some other dependent timings changed. Everything else stays the same. That can be a quick test