Since everyone is sharing now I suppose i'll put what I've come up with out here. Running -125mv 470 Nitro Sapphire 8GB with Samsung memory with ETH hitting between 28.5MH/s to 29.2MH/s @1140 cor and @2100 mem pulling around 920watts at the wall with 6 GPU per rig. On XMR hitting 785h/s to 795h/s @1170 cor and @2100 mem pulling around 660 watts at the wall with 6 GPU per rig. Also running ethOS 1.2.0. Im here to learn more about the mistakes I made on the mod and see what others in the community have come up with.
Here is the strap I've put together:
777000000000000022CC1C00106A5B47C0570E16B08C05090068C70014051420FA8900A00300000 0190D2F399D2D2E17
....
Looking forward to others input!
Here is the strap I've put together:
777000000000000022CC1C00106A5B47C0570E16B08C05090068C70014051420FA8900A00300000 0190D2F399D2D2E17
....
Looking forward to others input!
Cleaned it up for you.
Code:
--> HEX strap: 777000000000000022CC1C00AD695D47C0570E16B08C05090048C70014051420FA8900A003000000190D2F399D2D2E17
--> MC_SEQ_WR_CTL_D0
DAT_DLY = 7, DQS_DLY = 7, DQS_XTR = 0, DAT_2Y_DLY = 0, ADR_2Y_DLY = 0, CMD_2Y_DLY = 0, OEN_DLY = 7, OEN_EXT = 0
--> MC_SEQ_WR_CTL_D1
DAT_DLY = 0, DQS_DLY = 0, DQS_XTR = 0, DAT_2Y_DLY = 0, ADR_2Y_DLY = 0, CMD_2Y_DLY = 0, OEN_DLY = 0, OEN_EXT = 0
--> MC_SEQ_PMG_TIMING
TCKSRE = 2, Pad0 = 0, TCKSRX = 2, Pad1 = 0, TCKE_PULSE = 12, TCKE = 12, SEQ_IDLE = 7, Pad2 = 0, TCKE_PULSE_MSB = 0, SEQ_IDLE_SS = 0
--> MC_SEQ_RAS_TIMING
TRCDW = 13, TRCDWA = 13, TRCDR = 26, TRCDRA = 26, TRRD = 5, TRC = 71, Pad0 = 0
--> MC_SEQ_CAS_TIMING
TNOPW = 0, TNOPR = 0, TR2W = 28, TCCLD = 3, TR2R = 5, Pad0 = 0, TW2R = 14, TCL = 22, Pad1 = 0
--> MC_SEQ_MISC_TIMING
TRP_WRA = 48, Pad0 = 2, TRP_RDA = 12, TRP = 22, TRFC = 144
--> MC_SEQ_MISC_TIMING2
PA2RDATA = 0, Pad0 = 0, PA2WDATA = 0, Pad1 = 0, FAW = 8, TREDC = 2, TWEDC = 7, T32AW = 6, Pad2 = 0, TWDATATR = 0
--> MC_SEQ_MISC1
-- MR0
WL = 4, CL = 23, TM = 0, WR = 25, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0
-- MR1
DS = 0, DT = 1, ADR = 1, CAL = 0, PLL = 0, RDBI = 0, WDBI = 0, ABI = 0,
RES = 0, BA0 = 0, BA1 = 1, BA2 = 0, BA3 = 0
--> MC_SEQ_MISC3
-- MR4
EDCHP = 10, CRC WL = 7, CRC RL = 3, RD CRC = 0, WR CRC = 0, EDCHPi = 1, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 1
-- MR5
LP1 = 0, LP2 = 0, LP3 = 0, PLL/DLL BW = 0, RAS = 0, BA0 = 0, BA1 = 1, BA2 = 0, BA3 = 1
--> MC_SEQ_MISC8
-- MR8
CLEHF = 1, WREHF = 1, RFU = 0, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0
-- MR7
PLL Stby = 0, PLL Fclk = 0, PLL DelC = 0, LF Mode = 0, Auto Sync = 0, DQ PreA = 0, Temp Sensor = 0, HVFRED = 0,
VDD Range = 0, RFU = 0, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0
--> MC_ARB_DRAM_TIMING
ACTRD = 25, ACTWR = 13, RASMACTRD = 47, RASMACTWR = 57
--> MC_ARB_DRAM_TIMING2
RAS2RAS = 157, RP = 45, WRPLUSRP = 46, BUS_TURN = 23
--> MC_SEQ_WR_CTL_D0
DAT_DLY = 7, DQS_DLY = 7, DQS_XTR = 0, DAT_2Y_DLY = 0, ADR_2Y_DLY = 0, CMD_2Y_DLY = 0, OEN_DLY = 7, OEN_EXT = 0
--> MC_SEQ_WR_CTL_D1
DAT_DLY = 0, DQS_DLY = 0, DQS_XTR = 0, DAT_2Y_DLY = 0, ADR_2Y_DLY = 0, CMD_2Y_DLY = 0, OEN_DLY = 0, OEN_EXT = 0
--> MC_SEQ_PMG_TIMING
TCKSRE = 2, Pad0 = 0, TCKSRX = 2, Pad1 = 0, TCKE_PULSE = 12, TCKE = 12, SEQ_IDLE = 7, Pad2 = 0, TCKE_PULSE_MSB = 0, SEQ_IDLE_SS = 0
--> MC_SEQ_RAS_TIMING
TRCDW = 13, TRCDWA = 13, TRCDR = 26, TRCDRA = 26, TRRD = 5, TRC = 71, Pad0 = 0
--> MC_SEQ_CAS_TIMING
TNOPW = 0, TNOPR = 0, TR2W = 28, TCCLD = 3, TR2R = 5, Pad0 = 0, TW2R = 14, TCL = 22, Pad1 = 0
--> MC_SEQ_MISC_TIMING
TRP_WRA = 48, Pad0 = 2, TRP_RDA = 12, TRP = 22, TRFC = 144
--> MC_SEQ_MISC_TIMING2
PA2RDATA = 0, Pad0 = 0, PA2WDATA = 0, Pad1 = 0, FAW = 8, TREDC = 2, TWEDC = 7, T32AW = 6, Pad2 = 0, TWDATATR = 0
--> MC_SEQ_MISC1
-- MR0
WL = 4, CL = 23, TM = 0, WR = 25, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0
-- MR1
DS = 0, DT = 1, ADR = 1, CAL = 0, PLL = 0, RDBI = 0, WDBI = 0, ABI = 0,
RES = 0, BA0 = 0, BA1 = 1, BA2 = 0, BA3 = 0
--> MC_SEQ_MISC3
-- MR4
EDCHP = 10, CRC WL = 7, CRC RL = 3, RD CRC = 0, WR CRC = 0, EDCHPi = 1, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 1
-- MR5
LP1 = 0, LP2 = 0, LP3 = 0, PLL/DLL BW = 0, RAS = 0, BA0 = 0, BA1 = 1, BA2 = 0, BA3 = 1
--> MC_SEQ_MISC8
-- MR8
CLEHF = 1, WREHF = 1, RFU = 0, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0
-- MR7
PLL Stby = 0, PLL Fclk = 0, PLL DelC = 0, LF Mode = 0, Auto Sync = 0, DQ PreA = 0, Temp Sensor = 0, HVFRED = 0,
VDD Range = 0, RFU = 0, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0
--> MC_ARB_DRAM_TIMING
ACTRD = 25, ACTWR = 13, RASMACTRD = 47, RASMACTWR = 57
--> MC_ARB_DRAM_TIMING2
RAS2RAS = 157, RP = 45, WRPLUSRP = 46, BUS_TURN = 23
Lots of options.. lots of things to fine tune..
Thanks will give it a shot when I get back on a computer.
Here is the strap I've put together:
777000000000000022CC1C00106A5B47C0570E16B08C05090068C70014051420FA8900A00300000 0190D2F399D2D2E17
The timings from wolf and ohgodagirls vbios decode tools release:
777000000000000022CC1C00106A5B47C0570E16B08C05090068C70014051420FA8900A00300000 0190D2F399D2D2E17
The timings from wolf and ohgodagirls vbios decode tools release:
You should update to the version with my changes that show CAS timing. I see you're using CL=22. With Samsung CL=21 I was getting errors at 2100 (OK at 2000). I'll give 22 a try.
Here's what I was using @2000:
555000000000000022CC1C00CE595B3ED0570F1531CB2409004007000B0314207A8900A00300000 0170F2E36922A3217
I am seeing HW errors with the current mod I'm running but not an exponential amount that affects performance on the pool hash rate. I will be able to test more once I get back to my computer.
Hint: MC_SEQ_MISC_TIMING
EDIT: OhGodAGirl format:
Quote
typedef struct _SEQ_MISC_TIMING_FORMAT
{
uint32_t TRP_WRA : 6;
uint32_t Pad0 : 2;
uint32_t TRP_RDA : 6;
uint32_t TRP : 6;
uint32_t TRFC : 11;
} SEQ_MISC_TIMING_FORMAT;
Expected format:{
uint32_t TRP_WRA : 6;
uint32_t Pad0 : 2;
uint32_t TRP_RDA : 6;
uint32_t TRP : 6;
uint32_t TRFC : 11;
} SEQ_MISC_TIMING_FORMAT;
Quote
5:0 TRP_WRA = 0x0
13:8 TRP_RDA = 0x0
19:15 TRP = 0x0
28:20 TRFC = 0x0
I must admit that I think OhGodAGirl's format looks more like it.13:8 TRP_RDA = 0x0
19:15 TRP = 0x0
28:20 TRFC = 0x0