Hint: ARB_DRAM_TIMING.ACTRD/ACTWR can go lower 
I think I've figured out ACTRD. It's the delay between successive READ commands to the same row(page). It doesn't seem to be mentioned anywhere in the Hynix datasheet, nor in any of the GDDR product briefs I've looked at. I had incorrectly assumed that back-to-back reads from the same row were possible. With ETH mining (on AMD cards) each DAG access results in 2x 32-byte reads from 2 GDDR chips (128 bytes total).
The delay between ACTIVATE and READ is RCDR, and in the default Samsung straps use ACTRD = RCDR + 1. Knowing the way DRAM works, ACTRD should be much lower than RCDR, but by how much? A paper by nVIDIA suggests ~50%. https://www.cs.utah.edu/~dkopta/papers/DRAM-SIGGRAPH14_post.pdf
I tried reducing ACTRD to 16, and while it seems stable so far, the speed improvement is tiny (less than 0.5%). So is this Samsung strap as good as it gets for Eth mining?
777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 010103139962C3617
There are a few more things that can gain you additional hash but won't be much. The best I did for my MSI Armor 4G 470 was 30.2 at 1148/2075 but was unstable due to high mem temp(no heatsinks on the modules...). You might try lowering tRCDR, but based on my exp...it will throw more errors, also tRC a few bits "might" improve 0.1% which is irrelevant(why risk stability to gain such a small improvement). Try setting WR(Write recovery) 1 bit after CLmrs...or don't...Testing, testing, testing.