So, looking into this whole mining with fpga system, and this code you people are working on, what is the required Logic cells/gates required for a full roll out? also whats the smallest unit you can get it running on? (the bare minimal for a half roll out (what ever you call it?))
I just want to dip my toe into the FPGA mining with a cheap and nasty chip set

just tell me to piddle off else where if its the wrong spot to ask
AJRGale,
I think you'll want at least a Spartan6 LX150. This is the cheapest device I would use. I would only run a fully pipelined implementation -- one that can do one hash per clock cycle. If you can get a hold of a Kintex7 or Virtex7 board you'll be a lot better because you can instantiate more miners.
fpgaminer has posted a lot of useful code on github.
I don't speak Altera, so not sure on specific devices.