Re: Official Open Source FPGA Bitcoin Miner (Smaller Devices Now Supported!)

Quote from: TheSeven on June 03, 2011, 10:07:41 PM

Now I have: http://dl.dropbox.com/u/23683845/fpgaminer-virtex5.zip
You'll need to adjust the line "constant DEPTH : integer := 6;" (2^n pipeline stages) in top.vhd.

Hi All. I am trying to implement the following on a Virtex 6. DCMs are no longer used on the Virtex 6 and have been replaced with MMCMs. So far I have swapped the DCM for an MMCM and am able to implement the design. But when I try to run the python script, it fails. I get a "Got bad message from FPGA: 240". I would appreciate any guidance you could provide. Thanks.