For what it's worth, I used 5SGXEA7H1F35C1 and got 11% utilization (~8 cores?), and Fmax >200MHz.
BTW: was this the design found in the rtl directory or in some of the projects?
I will try to re-run it as my timing result can't be correct...
I checked my design and my clock was not properly constrained due to a syntax error in my SDC file. I ran it with the corrected SDC file.The result is still not great: 185.84 MHz. Again, it was the plain unrolled design from the "rtl" directory without any specific optimization. However, the speed difference could be due to the difference between the C1 and the C2 device.