Post
Topic
Board Hardware
Re: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)
by
fpgaminer
on 25/04/2013, 00:14:13 UTC
Quote
When I replaced dsp_e with adder I got 302 MHz
I find it odd that your Fmax is dropping when you replace the DSPs with LUTs.  You may want to fiddle around with Vivado's settings to make sure register retiming (or whatever Vivado calls it) is enabled.  Alternatively, implement the adders as two stages of 16-bits each.  Since the DSPs that are being replaced are two stage (or three) anyway.

Also, for dsp_t1p, it would be best to replace both dsp_t1p and compressor_t1p with a single LUT adder, since the LUT fabric can implement 3 way additions just as efficiently as 2-way addition.