Re: Official Open Source FPGA Bitcoin Miner (Smaller Devices Now Supported!)
I now have a bitfile for the atlys board (spartan 6 - lx45) with depth:=2 and 50mhz
The only problem is, that miner.py refuses to communicate over the serial port.
It detects the core, but when it starts "Measuring FPGA performance..." it produces and timeout: "Timed out waiting for FPGA to accept work"
@TheSeven: any idea how to debug or solve the problem? is the miner.py code working for all depths and frequencies?
You'll need to adjust the pin locations for clk_in, rx and tx in the UCF file, and adjust the clock divider for the serial port for the 50MHz frequency.The only problem is, that miner.py refuses to communicate over the serial port.
It detects the core, but when it starts "Measuring FPGA performance..." it produces and timeout: "Timed out waiting for FPGA to accept work"
@TheSeven: any idea how to debug or solve the problem? is the miner.py code working for all depths and frequencies?
Replace "10000010001" with "0110110010" and "11000011001" with "01010001011" in uart.vhd.
And I should probably publish the new version of my miner, it now supports multiple pools, long polling, etc.
TheSeven, can you give some lines on how to calculate the deviders, any formula?