I'm trying to compile the "projects/X6000_ztex_comm4" myself, for devices "xc6slx150, speed -3", under Xilinx ISE v13.4, and code from Github without any modification.
using default compiling option from "xilinx_fpgaminer.xise", under the goal of "Timing Performance", the placement failed. after change goal to "Minimum Runtime", the project compiled successfully, but the timing constrains can't be met. from the PAR report, the clock speed is only 153MHz (cycle 6.54ns). I'd like to ask what optimization options need to use to achieve > 190MHz clock speed? please help me, thanks very much.
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_CLK_100MHZ | 10.000ns| 9.689ns| 13.082ns| 0| 633| 1456| 3690036|
| TS_dynamic_clk_blk_clkfx | 5.000ns| 6.541ns| N/A| 633| 0| 3690036| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Slice Logic Utilization:
Number of Slice Registers: 84,129 out of 184,304 45%
Number used as Flip Flops: 84,129
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 50,798 out of 92,152 55%
Number used as logic: 35,040 out of 92,152 38%
Number using O6 output only: 15,507
Number using O5 output only: 581
Number using O5 and O6: 18,952
Number used as ROM: 0
Number used as Memory: 3,297 out of 21,680 15%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 3,297
Number using O6 output only: 449
Number using O5 output only: 0
Number using O5 and O6: 2,848
Number used exclusively as route-thrus: 12,461
Number with same-slice register load: 12,036
Number with same-slice carry load: 425
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 15,049 out of 23,038 65%
Nummber of MUXCYs used: 22,144 out of 46,076 48%
Number of LUT Flip Flop pairs used: 58,734
Number with an unused Flip Flop: 959 out of 58,734 1%
Number with an unused LUT: 7,936 out of 58,734 13%
Number of fully used LUT-FF pairs: 49,839 out of 58,734 84%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%