The performance numbers sound reasonable. I have no idea why he only gets 8MHz, but this sounds like it can be improved. For a full pipeline you need roughly 100K flipflops plus all the logic. 100 times that would be 10M flipflops plus logic, which would be a rather big ASIC, but it's certainly possibly.
He can't get over due to hazards . The propagation delay will be way too big to get any higher frequency.
This can't be true if we manage to get >100MHz even on FPGAs. 8MHz sounds like the algorithm isn't pipelined at all, and calculates a hash in a single clock cycle, which is a waste, as latency doesn't matter here. What matters is throughput, and if you can get more than 20 times the throughput with just a couple of additional flipflops, you shouldn't bother about 128 clocks of latency.