Re: Klondike - 16 chip ASIC Open Source Board

It looks like the hash chip sends back the report data asynchronously. Is a PIC controller capable of concurrently clocking in results from multiple chips?

It's a wired OR bus, all outputs join together into one PIC input. The PIC does have a UART and amazingly I just hooked REPORT_P to that pin.

What's even better is it has IOC (interrupt on change) so I don't have to poll it.

Are you assuming only one chip will report data at a time (i.e. data is never being sent concurrently by more than one chip)? I have a feeling all chips will report some kind of status not just when a good nounce was found. But I guess we won't know for sure until the communication protocol is released.

At this time I believe it reports only found nonces and the chances of collision are slim. I'm basing this off how Icarus worked. Looking at the driver it's likely it also reports back the full midstate and data, which I can ignore since I have that in RAM already. If the driver was smart it wouldn't need that info back either. ie. it stores that info for each known miner module. I think we have to assume this since Avalon has all 10 ASIC chips wired this way. They all connect to a 470 ohm resistor tied high and a buffer to go off board to the FPGA. If the ASIC is "smart" it can detect traffic by watching before using the bus, but I don't know if it does that. It doesn't seem very efficient either to send the midstate and data all back again but if the FPGA cannot store it for each module then it would have to since the Avalon driver expects to read it back.