I managed to fit one SHA256 round, one hash per clock, into about 30k LUTs + 13k registers on a Cyclone, although I never validated this design because my FPGA only has 17k LUTs. So, if I didn't mess up (which I can't really tell...) this would mean 60k LUTs + some interfacing. I verified the core idea behind this in a non-FPGA simulation, and then implemented the idea in Verilog.

Unfortunately the larger dev boards are a bit too expensive for my taste, so this project is on halt. If anyone is willing to loan one to a complete stranger, I'm all up for it We could meet first. I live in East of England, pm me if you wish.