Overall Project status:
Hardware:
Schematic - done
PCB Design - in progress
Firmware:
USB host interface - testing (yes, cgminer thinks the pic32 is an Avalon)
CAN - in progress
Chip interface - in progress
Hi burnin,
what about the pre-calculation mentioned in the ASIC datasheet (section 4.2)? Isn't their FPGA doing that? Or cgminer does that automatically? I'm not sure how difficult is to compute that for each ASIC when it is doing 300 Mhash. I don't see the nonce mentioned there, so probably only one pre-calc is needed for each chain of 10-20 ASICs?