single chip 100Mhash/s?
What about evolving the hardware to do the hashing rather than writing it as straight VHDL?
I had a good idea about using hadoop clusters to run the fitness tests for the evolutionary algorithm testing.
For those who have no clue what i am talking about, read the article about the professors that got an fpga to recognize the difference between two tones with way less than 100 gates and no CLK.
http://fsweb.olin.edu/~mchang/research/documents/seminar/evolve2k2/evolve.ppthttp://www.cogs.susx.ac.uk/users/adrianth/ade.htmlI always had a thought that evolving the circuits would be a way to find really fast ways of "cracking" various hashing algorithms, as well as making really tiny encoders and decoders for various projects.
Anyhow, i enjoyed this thread.
You're on the right track - the synthesis of ASIC or FPGA circuitry from Verilog or VHDL code is very very good these days, but there are ways to make things better particularly when you are building an ASIC.