50 GH for 180 W seems really bad for 14 nm. 3.6 W / GH. Asicminer chips are 7W/GH and they are like 110nm.  A 2x increase in performance/power seems like very little for an 8x reduction in process size. Intel CPUs increased in performance from about 0.4 Gflops to 100 Gflops at the same power level with a comparable 8x reduction in process size (from 180 nm to 22 nm), a performance/power increase of 250x compared to your 2x...

Also no reason to build this on a PCIE interface... the data throughput is not needed, and it unnecessarily limits people to just a few per computer or requires expensive and finicky adapters/risers/extenders/etc, when it could just be USB.

Based on this, given that a real company spending millions on such a project would know the above, I'm gonna go out on a limb here and say this isn't real...