Clock distribution for the ASIC cardsUPDATE: I chose a third option, a cheaper one. See end of this post
So now I've taken a look at the distribution of the clock. A few things were clear from the start. I like well terminated clock lines, low EMI and low cost.
I also like a clean clock edge transition between 0,8V and 2,0V (traditional 3,3V cmos thresholds). If it's not, an extra, narrow, pulse could be sent to the ASIC, which would not be nice to it's PLL.
Also fast edges tend to decrease jitter, but fast edges mean you'll get issues with reflections on your transmission lines. No idea if the avalon clock input has a shmitt trigger input.
Also, no layer changes, vias represent an impedence change. Which can cause increased reflections and extra EMI.
Anyway, I've narrowed it down to two setups.
The first shows a single clock source which via a 1:3 fanout buffer sends it to logic buffers with shmitt trigger inputs located near every asic.
Those three fanout lines are daisychained without(with minimal) stubs and is terminated by an RC network.
http://s10.postimg.org/mnua5f1mh/clocknet_daisy_chained_RCterm.jpgthousand hours in paint.netI've done some simulations in LTspice to estimate how the clock would look like at the end.
I take 0,3nsec as the worst(fastest) case rise time, as many manufacturers ony talk about typical or maximum rise/fall times. Understandable, as that constrains the usable frequency range.
But for me, wanting to limit reflections, I want a buffer that is just fast enough to retain a decent puls form.
I've simulated the daisychain by seperating the transmission line with capasitors, representing the input pads of the buffers.
Distance is set by the propagation delay of the line, according to my calculator a 75Ohm line delays about 56psec per centimeter.
I always used 50psec per centimeter as a rule of thumb.
To take account for process variations I did three simulations with varying output imedances and line impedances.
The pictures are clickable.
http://s2.postimg.org/l93i3tcr9/Sim_parallel_RCterm_daisychain_normal.jpg Normal condition, well matched impedance
http://s7.postimg.org/ah24l3qp3/Sim_parallel_RCterm_daisychain_upper_worst.jpgWorst case high impedance.
http://s15.postimg.org/eiv91plmf/Sim_parallel_RCterm_daisychain_lower_worst.jpgWorst case low impedance.
I'm not to happy with that, the position closest to the source doesn't transfer the 0,8V to 2,0 and back, too well.
_______________________________________________________________________________
_______________________________________________________________
Now to the second part, point to point connections. A single clock goes to a single, 1:12 fanout buffer, which sends a dedicated clock line per asic across the board.
They also have a resistor near the source to terminate the line. Rdriver+Rseries = Zline in an ideal world.
http://s7.postimg.org/6gm90r2ej/clocknet_fanout_point_to_point.jpgI left out the series resistors.I simulated the point to point connection, the resistor at the end reprisents the input resistance(resulting in leakage current) of the clock input of ASIC.
The capacitors represent parasitics of the pads, the chips are located on.
I used a 1nsec delay, which is about 20cm in length, while in reality we'll probably end up at half of that as a maximum.
The pictures are clickable.
http://s12.postimg.org/4qzvu3h2x/Sim_series_Rterm_pointtopoint_normal.jpgNormal, well matched.
http://s10.postimg.org/sc11fomwl/Sim_series_Rterm_pointtopoint_upper_worst.jpgWorst case high impedence.
http://s23.postimg.org/ehrn43p7b/Sim_series_Rterm_pointtopoint_lower_worst.jpgWorst case low impedance.
While not perfect, the 0,8V to 2,0V and back transition looks way better. But routing all those lines might make routing the 1,2V connections more difficult.
Also there is probably increased EMI.
Conclusion: I'll pick the second, point to point solution. Even with it's drawbacks it delivers a more robust connection. And that was my main priority.
Parts chosen: 13x generic 1% 0603 resistors of 37Ohm
Oscillator: CTS CB3LV-3C-32M0000 (it's a bit large, but it's the cheapest I could find, so whatever)
Fanout 1:12 buffer: texas instruments CDCLVC1112PWR, A bit overkill in the frequency department, but it keeps averything on one chip, that's what I was going for.
Combined price, around 6 to 7. Perhaps I could find a cheaper fanout buffer.
_______________________________________________________________________________
_______________________________________________________________
UPDATE:I was not happy with the cost so I chose some alternatives. It did require a second chip though.
http://s11.postimg.org/hsl274aab/clocknet_fanout_point_to_point_2.jpgParts chosen:1x Oscillator CTS CB3LV-3C-32M0000 (no need to change it) 1,14
1x Fanout buffer 1:10 Pericom PI49FCT3807CQE (old and cheap, but for these frequencies it's good) 1,16
1x Fanout buffer 1:4 OnSemi NB3N551DG (a bit better and more expensive, but more energy efficient and saves board space) 1,57
13x generic 1% 0603 resistors of 59Ohm (higher value than befor due to the lower output impedance) cheap
So we'll end up cheaper, like at 4 or so.
These buffers have individually specified Vout_high and Vout_low voltages at a certain current. From there a output impedance could be calculated.
Typical of these CMOS outputs (pmos/nmos totem pole) the Vout_high has a higher impedance than the Vout_low. This makes finding a proper termination more difficult.
The low to high edge has a diffrent output impedance than the high to low edge. I couldn't recreate that quickly in ltspice, so in the end I ran it all twice, changing the impedance.
59Ohm is a bit to high, but provides a safety margin in case the trace impedance turns out quite a bit higher than expected.
Please keep in mind that these simulations only show one edge correctly.
http://s24.postimg.org/abh3b22jl/Sim_series_Rterm_high_to_low_high_imp.jpgHigh to low edge, high trace impedance.
http://s21.postimg.org/g8mra4l03/Sim_series_Rterm_high_to_low_low_imp.jpgHigh to low edge, low trace impedance.
http://s10.postimg.org/3tm25l5o5/Sim_series_Rterm_low_to_high_high_imp.jpgLow to high edge, high trace impedance.
http://s24.postimg.org/lkdnht9wh/Sim_series_Rterm_low_to_high_low_imp.jpgLow to high edge, low trace impedance.
