https://mega.co.nz/#!GIF1gYZK!M_8JowhsGc6wc2b3fsRHVCdst5w8UC0M2yq1RgHwDV8

Here's source code "as is" of all my fpga-related work.

There's hardmacro placer and
btcser is core that gave 300 Mh/s+
and
different other tries - say 4 sha256 fully unrolled cores example.

I have given sources already to some people expecting them to make bitstreams for say ZTEX boards, but it seems that they failed to understand what there is.
You may try to accomplish that if you're good enough. Or may forward it to those who you believe are good enough and would like to spend time on this.
I promised actually long time ago to make it opensource, so I am keeping this promise, but unfortunately to make it usable it should be ported to other
device interface and I don't have time to do that.

BTW, asic layout some time in the future will be opensourced as well. So this will be likely end-game against any competition here, as when they get to master full-custom layout - it will become opensource stuff