From reading the firmware source and looking at the released datasheet, the BFL chips interestingly do not have certain SHA-256 constants hardwired. The firmware is responsible for setting the SHA-256 initial hash value for the first hash, as well as the padding and length of both the first and second hashes.

What this means is that (for example) if an extra field were to be appended to the block header, the BFL chips could handle this change (via. a firmware upgrade), but the Avalon chips couldn't. This also means that the BFL chips are slightly less-than-optimal (I have no idea how much less than optimal), since some extra gates will be required to handle the possibility that those "constants" can change.