Within an ASIC, this would manifest as increased die area or power consumption. But I have no experience with ASIC design, so for all my ignorance it could be an insignificant 0.0001% increase or an embarassing 10% increase.
My gut isn't all that ASIC experienced, but FWIW it says fairly insignificant, few tens of extra gates for the few millions total.... I'd put a range of 0.01% to 0.001% on it.