Re: [ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE!
Normally, IOREF is set with a restistor divider to half
IOVDD (normally 1V8). To make the board simpler, IOREF
was connected to core voltage.
http://imgur.com/QZYoGDQ
Core voltage was adjusted between 0V59 and 0V83 V and operation
of the chips remained normal.
Leszek/bitfury, can this be done on the miner board also?
Reduces the wiring a bit.
intron
IOVDD (normally 1V8). To make the board simpler, IOREF
was connected to core voltage.
http://imgur.com/QZYoGDQ
Core voltage was adjusted between 0V59 and 0V83 V and operation
of the chips remained normal.
Leszek/bitfury, can this be done on the miner board also?
Reduces the wiring a bit.
intron
Yes. This is why IOREF pin is there (near VDD
. If you don't use external clock and spi is slow enough (you don not worry about width distortion) - it will work just perfectly. But when you slice CMOS signals not exactly at 50% level - then - you would encounter slight width distortion caused by sampling differences.