OK, brass tacks time.  Try this.  Put 100k of your flops in a ripple counter configuration.  Tie each one's power supply and ground pins to the next with 20 milliOhm to simulate resistive drop in your metal lines.  I'm generously estimating your power rail metal as a big fat 2um run in a 20-50 nm process.  I'm OK with you tapping in higher metal every few thousand gates, but you can't cheat on via resistance.  50 Ohm/via at least.

Now take your 100k ripple counter and clock it at 1Ghz.  Take it's output and build yourself a simple compare - Xor is fine, but you've got to remember the supply resistances in this stage as well.  Compare the 1GHz counter with the output of a second counter running at a non-evenly divisible frequency, say 77MHz.  Then clock this compare result into one final register at 1GHz as well, and for extra points you'll want to buffer the clocks between the two counters - your real chip would be a big ass tree, so no ideal wires in the clock lines.

Tell me how many times you get a false match running at ~300mV noise margin.  The 2^N transitions on your fast ripple counter are going to demolish your rail, easily dropping 150-200mV and completely corrupting any noise margin you think you have, even at this tiny scale.  Then re-sim at 125C.