PLL might be a good place to start looking. Just make sure your PLL maintains a good lock.
I wouldn't be at all surprised if now and then the PLL unlocks and the clock shifting causes error results. I would also guess that is more likely to occur closer to the clock limit values, eg. ~512 where I am now, and by moving up to 600 it has more stability. (@half clock is 128 vs 150).
Next board revision will have that ferrite bead on the PLL power inputs, and can only help. I don't know if one of the debug outputs maybe indicates PLL lock but I otherwise have no way to know. It would be nice to know what the 2 debug outputs are but I haven't seen any docs about them.
In Xilinx FPGAs the PLLs are very picky about the multiplier. eg the multiplied clock must be between 800MHz and 1600MHz. With a 100 MHz input you would never use a multiplier of 2 and a divider of 1 to get 200MHz, you would use a multiplier of 10 and a divider of 5 to put the multiplied clock into the valid range. It might be worth sweeping the mutliplier range to see if certain values perform better.