If you have 5 chips you could put 4 of them on the K16 board and it should work quit well.
For example using the current design you would place the ASIC's at U6,U8,U9,U11.
Maybe use the extra chip in a K1.
That's right but also if you add the 5th chip it will break nonce ranges as if 6 are present which will still work but will leave 1/6th of the ranges unchecked. This doesn't cause problems and since any range is good as another, as long as each chip is checking unique ranges, it's still efficient. A job will finish slightly more often (4 split vs 6 split), so that's the only overhead timing loss.
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As I'm sure you know, the amount of each nonce range processed doesn't matter.
ckolivas also solves the problem of not getting exact hash statistics by simply counting the number of nonces found - since of course on average, you'll find one valid 1diff nonce per full nonce range processed.
Although over a short time frame this isn't very accurate, if you are hashing in the 10s of GH/s (or more) this is still good enough.