If I see right, each hashing module in reference design got 20pin (10x2) header. Most of pins are connected to Vcc and GND. The most interesting signals are two diferential pairs config and report. Chips on hashing module are connected serial on config, and parallel on report. And it's I wanna try to connect to FPGA's IO in the first step with single chip or couple of chips. Of course I have to connect Vcc, GND and CLK to chip.
The next step may be a simple reduction between FPGA-based machine and reference design's hashing module, or another hashing module.