Sigh, this is (sort of) what the Icarus bitstream does also - if 2 nonces arrive at the same time, you lose one.
The only catch of course is that "at the same time" can be a long time frame with regards to hashing nonces ... which increases how often it happens.
Hopefully here "at the same time" is a VERY small window.
Just roughly figured this...
Assuming we accept a dead zone then reading by the PIC can be at it's full speed using the UART input in master mode. I didn't check but maybe 1 MHz is feasible, so 32 uS roughly for dead zone, plus re-arm time, say 8uS, so say 40uS. Since a nonce takes 9.1 uS (@450 MHz clk / 128 output speed), that means potentially the 4 nonces after a result nonce are dead. But nonces could occur on any of 16 chips so that's x16 = 64 nonces could be found during a dead zone making the probability 64/2^32 of that happening, ie. 0.0000015%. Something most users can live with in terms of income loss.
Not sure if that's right but my first look at it.
Also, I'm not sure what the max data rate on the UART is. It's not in the timing specs for the PIC. If it can handle 4 MHz then the dead zone is more like 12uS. The firmware gains mostly because it has control of handling data rather than being at the mercy of random ASIC output. Multiple nonces could be received by the SRAM when armed but when the PIC gets around to handling them the dead zone would occur.