usart timing is at page 375 of the pic datasheet - not what you searched in detail -but still interesting.
page 270 and page 271:
Maximum set-able baud-rate:
Desired Baud Rate = FOSC / (4 * (SPBRGH:SPBRGL +1))
48MHZ / 4 = 12MHz - thats "fast"
Ok. So we assuming we refill the UART close to optimally then we could probably get the dead zone to (32+8+16)/12 = 5, say 6uS maybe. Which should be a very, very tiny loss in nonce data, maybe around 0.0000015/5 = 0.0000003%. And maybe double if your average work has 2 nonces but it seems like most have 1 or 2, and a few have 3.page 270 and page 271:
Maximum set-able baud-rate:
Desired Baud Rate = FOSC / (4 * (SPBRGH:SPBRGL +1))
48MHZ / 4 = 12MHz - thats "fast"
So it's probably not worth delaying nonces to avoid the dead zone. You could lose more due to block change if delayed. The main thing is it completely frees up the IRQ timing constraints.
Your % aren't quite correct (when you divide the work up, the range for each is of course the division, not 2^32), but the numbers are small enough that indeed it appears it's better to lose a nonce once in a while than slow things down by more than that resolving the problem.
Average nonce per 2^32 is of course 1.
However, 4 isn't all that rare (hmm I think I'll add a stats counter for the BFLSC to see how often >1 does happen - that one's the easiest to do it)