Re: Official Open Source FPGA Bitcoin Miner (Smaller Devices Now Supported!)
Thanks, it work fine,
but i get only 6.253394 MH/s
My FPGA is Virtex IIPro XC2VP50 and project settings are:
miner clock frequency = 50 MHz
DEPTH = 3
In your opinion, is 6 MH/s correct value for this project settings?
or did I do something wrong?
but i get only 6.253394 MH/s
My FPGA is Virtex IIPro XC2VP50 and project settings are:
miner clock frequency = 50 MHz
DEPTH = 3
In your opinion, is 6 MH/s correct value for this project settings?
or did I do something wrong?
DEPTH = 3 means 2^3 = 8 pipeline stages for the 64 SHA256 rounds, so each nonce will take 64 / 8 = 8 clock cycles. At 50 MHz that's 50 / 8 = 6.25 MH/s.