I am not a semiconductor guy, but just my discussions with folks that are suggest that the "design rules" and associated tool chains change on a regular basis as the node size shrinks. What that means to me is that the "rules and tools" for a 40nm process don't work for a 28nm process which don't work at 16nm. I think that means that your idea of developing with "cheap" process and then shrinking down won't work since the Fab for 16nm can't use "masks" from a 40nm process. Voltages are all wrong, leakage current and a whole host of things that don't manifest at 40nm become hugely important at 16nm. I expect the testing and packaging also changes.
I know that very well.
The arrangement of transistor gates required to implement a double SHA-256 hash would not change. The implement would change for the target process node and Fab.
By demonstrating that your transistor level design is correct, the risk is dramatically reduced. It's not zero because, as you say, the implementation at each node would require a unique design layout.
Would it really move the need on the costs to implement a bitcoin hash chip? I can't say for certain. I can tell you that a surface discussion with somebody exposed to semi design won't give you a valid answer because they are thinking in terms of tool chains and standard cells that decouple you from the transistor level by several layers. It simply isn't industry standard practice. But results delivered by Bitfury make it clear it's the only way to be competitive in the crypto mining space.
Moderator's note: This post was edited by frodocooper to remove a nested quote.