Because Gen 1 is purely a rough draft to reach an ASIC race goal.
The chips will do their job, albeit be crude and unrefined.
This chip design is all about minimising risk and playing safe whilst delivering in a timeframe that meets ROI for their crowd sourced investors.
It's literally a prototype that future revisions will expand upon, of which there is a lot of room for improvement.
That doesn't really make a lot of sense, once the fixed cost is taken care of, what's the per-chip cost of running another set of wafers? The first run had to be priced in order to cover the (expensive) R&D costs. Sure, they could tweak the design but they'd need to run another set of masks, pretty expensive.
The other thing to keep in mind is that their design is probably pretty close to optimal. Outside of die shrink the amount of improvement per chip by tweaks probably isn't that great.
On the other hand, now that R&D is paid for, they can go ahead and lower the cost of their chips. Their Gen-2 could simply be 2x as many chips, running at a 75% slower clock, which should reduce power demand and thermal issues per chip - remember, the cooler silicon is, the lower the resistance, which means you get increasing returns on power and temperature if you can reduce power (lower energy from lower clock, means lower temperatures, which means even lower energy due to reduced resistance)