We've got info on
KNC's die size and the like, how about an update to the OP?
The link links to KnC's own news with fresh technical details and especially 43 mm x 43 mm die size.
I just can't believe the die will turn out to be that large. Nobody builds 43x43mm dies.
You didn't follow the link, did you?
That's a quad solution: four dies on one chip. Each one is 21.5 x 21.5 mm and should have 25 GH/s, but it gives us the same η value as one 43 x 43 mm die outputting 100 GH/s..
Everyone has followed the link. You are measuring the package area not the die area. There are no measurements associated with the ASIC section of that series of pictures. It is bizarre accounting to use the package size for one chip but the die sizes for all the others.