I'm starting to think that a process-invariant metric of power efficiency isn't possible -- at least not one that can be determined by testing (i.e. without the circuit schematics and layout parasitics, neither of which any vendor is ever going to release).

Bitcoin mining chips' power consumption is mostly dynamic power; there's no reason for a mining chip to have any idle circuitry.  Dynamic power is determined by voltage, activity factor, and capacitance.  Although voltage can be observed, figuring out the mix of activity factor vs. capacitance isn't really possible.  At the very least you'd have to know the circuit style (bang-bang-CMOS, Domino, or MCML, for example).

But the biggest problem by far is that parasitic capacitance scales in really funny ways across process nodes an even between fabs.  The ratios between gate capacitance, sidewall capacitance, and gate-to-source/drain capacitance all change in unpredictable ways across generations.  Pretty much the only thing that scales predictably is parasitic capacitance due to metal routing, but a in a well-routed mining chip this is a very small component of the overall parasitic capacitance (except maybe the sigma-function rotation wires).  The vast bulk of your power ought to be going towards charging and discharging diffusion+gate capacitance.

So I don't really think we'll ever be able to independently estimate how well a design's power efficiency will scale across generations of fabrication processes.